The fabrication of integrated circuits (ICs) involves the formation of features that make up devices, such as transistors and capacitors, and the interconnection of such devices to achieve a desired electrical function. Since the cost of fabricating ICs is inversely related to the number of ICs per wafer, there is a continued demand to produce a greater number of ICs per wafer. This requires features to be formed smaller and smaller to reduce manufacturing costs.
Features are formed using photolithographic techniques, which includes depositing a resist over a device layer which is to be patterned. The resist is exposed with radiation or light through a mask. For a positive type resist, the exposed portions of the resist layer are removed during development, leaving a patterned resist layer to serve as a mask for an etch to transfer the pattern of the mask to the device layer.
In conventional lithographic techniques, line edge roughness (LER) occurs in the patterned resist layer. LER refers to the sidewalls of the resist mask being not smooth. Causes for LER include, for example, poor image contrast, non-uniform distribution of resist components, or insufficient acid diffusion during exposure. LER can result in uneven or irregular transfer of pattern onto the substrate. As feature size becomes smaller, the irregular pattern transfer can cause various device issues, particularly with high density dynamic random access memory (DRAM) ICs. For example, irregular pattern transfer can cause variations in gate threshold voltage (VT), leakage, and degradation of retention time, thereby adversely impacting device performance, reliability, and manufacturing yields.
From the foregoing discussion, it is desirable to improve the transfer of a pattern onto a substrate during manufacturing process.